riscv – What is the effect of nop instruction in instret CSR (in RISC-V architecture)?

In the RISC-V spec, there is a CSR called instret and variants of it for the privilege modes. The spec says that instret is the number of retired instructions. I wonder about the effect of nop instruction on this register because it is not an operation. And, this brings me to another question too. When there is a case that nop is inserted to flush or stall internally by hardware due to some problems, should this/those nop instructions also be counted for instret?
Is that two behaviour officially certain or left to the developer?