[RFC PATCH v4 0/4] RISC-V Smstateen support
This series adds support for the Smstateen specification which provides a mechanism plug potential covert channels which are opened by extensions that add to processor state that may not get context-switched. Currently access to AIA registers, *envcfg registers and floating point(fcsr) is controlled via smstateen.
This series depends on the following series from Anup: https://lists.nongnu.org/archive/html/qemu-riscv/2022-05/msg00139.html Changes in v4: - Fix build issue with riscv32/riscv64-linux-user targets Changes in v3: - Fix coding style issues - Fix *stateen0h index calculation Changes in v2: - Make h/s/envcfg bits in m/h/stateen registers as writeable by default. Mayuresh Chitale (4): target/riscv: Add smstateen support target/riscv: smstateen check for h/senvcfg target/riscv: smstateen check for fcsr target/riscv: smstateen check for AIA/IMSIC target/riscv/cpu.c | 2 + target/riscv/cpu.h | 4 + target/riscv/cpu_bits.h | 36 +++ target/riscv/csr.c | 555 +++++++++++++++++++++++++++++++++++++++- target/riscv/machine.c | 21 ++ 5 files changed, 615 insertions(+), 3 deletions(-) -- 2.25.1
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