regex – how to use regexp in auto instantiation of emacs verilog mode , in auto template…?

i am instantiating some big modules, there are multiple ports , and i have declared some internal wire
now i want to use that internal wire into the instantiation using regexp.

i want this:-

module top (input in_a, input in_b, output out_c, output out_x,out_y,out_z);
wire mux_p,mux_q,mux_r;

    submodule1 u_submodule1 (/*AUTOINST*/
        .a(in_a),
        .b(in_b),
        .c(out_c),
        .p(mux_p),
        .q(mux_q),
        .r(mux_r),
    );
    
    submodule2 u_submodule2 (/*AUTOINST*/
        .i(in_a),
        .j(in_b),
        .x(out_x),
        .y(out_y),
        .z(out_z),
        
    );
    
    //logic

endmodule