Re: Generating a finite waveform using an external clock, and retriggering

What DAQ device are you using?  It needs to be one that supports buffered counter output operations.  Such support has been pretty common for devices designed and released within the last decade or so, but there are some exceptions.

The help file you linked was not as helpful as it should have been – things weren’t explained very well, IMO.  The operating mode illustrated there is one I haven’t personally tried and don’t know what devices do and don’t support it.  Are you sure that’s the mode you need, one where each incoming sample clock pulse causes the counter to advance by one sample in its array of high/low times?  And each of those specific high/low pairs might repeat indefinitely until the next external sample clock pulse arrives?

If so, then you *probably* also need to watch out for a case where 2 sample clock pulses arrive before the first high/low pair can finish generating.  I would expect that to produce an error.  I *do* know that in non-buffered mode, it’s an error to change high/low times on the fly before the previous pair has completed at least 1 full cycle.

I would expect that a more common use case for buffered output is one where *every* pulse timing high/low pair is defined by the buffer of values.  Then you would configure for “Implicit” timing which will simply advance through the set of high/low pairs in sequence.

Either way, any device that supports buffered counter output should also support retriggering and the Implicit timing option.  Presumably *some* devices exist that support the external sample clock approach shown on the help page, I just don’t know which ones they are.  But I’d bet they would also support the retriggering you want.

-Kevin P

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