processor – Wrong solution to a short RISC-V exercise

We are told that a RISC-V exercise with no data forwarding executes the instruction add x3,x2,x1, followed by sw x3, 16(x8). My answer was the following:

                |    1   2   3   4   5   6   7 
add x3,x2,x1    |   IF  ID  EX  ME  WB
sw x3, 16(x8)   |       IF  ID  EX  --  ME  WB

With the following reasoning: the first row being obvious, the sw instruction needs the correct content of the x3 register to know in which memory address to store the value (ME), hence it needs for the first instruction to WB the result into the x3 register i.e. we need to wait until the WB of the first row to move on to the ME of the second row. The correct answer, however, is this:

                |    1   2   3   4   5   6   7   8   9
add x3,x2,x1    |   IF  ID  EX  ME  WB
sw x3, 16(x8)   |               IF  ID  EX  --  ME  WB

I do not even understand why the second IF can’t run right after the first. Why is this the case? Why are my answer and reasoning wrong?