Pre-Silicon Verification and Validation Methodology Targeting Robust RISC-V Chip Designs (BSC)

A new technical paper, “Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL,” was published by researchers at Barcelona Supercomputing Center.

Abstract

“The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe’s capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, we present a holistic pre-silicon verification and validation (V&V) methodology targeting highly robust RISC-V chip designs. This paper provides an overview of BZL’s V&V approach, which integrates three complementary platforms: (1) a UVM-based verification environment to thoroughly validate RTL functionality; (2) an FPGA-based validation platform that enables system-level pre-silicon hardware-software RTL validation; and (3) a CI/CD flow that continuously automates build, deployment, and tests across these domains. By embedding these platforms into an industrial-grade V&V loop and exploiting large-scale CPU and FPGA hardware infrastructures, the BZL project enables continuous evolution of reliable hardware development and software integration. We believe that the BZL’s V&V flow represents a robust and scalable foundation for ensuring the pre-silicon functional correctness and system level validation of RISC-V chip designs, and can serve as a key enabler for strategic initiatives in Europe, such as EPI and DARE, and beyond.”

Find the technical paper here. April 2026.

Ahmed, Sajjad, Alexander Kropotov, Roberto Ignacio Genovese, Bernat Homs, Eloi Merino, Francesco Urbani, Henrique Yano et al. “Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL.” arXiv preprint arXiv:2604.27013 (2026).