HARV – Hardened RISC-V System-on-Chip

The growing reliance on electronic systems in critical fields such as space exploration, avionics, and high-energy physics requires highly reliable processors capable of withstand harsh radiation environments. These environments pose various radiation-induced effects, including Total Ionizing Dose (TID) and Single-Event Effects (SEE), which can result in both temporary and permanent system failures. This paper introduces HARV-SoC (Hardened RISC-V System-on-Chip), a fault-tolerant processor built on the RISC-V architecture, specifically designed for dependable performance in radiation-prone environments. HARV-SoC employs hardware fault-tolerance mechanisms incorporating redundancy and error correction strategies to mitigate soft errors effectively. The design was validated through fault injection simulations and real-world irradiation tests with neutron, proton, and mixed-field radiation. The experimental results reveal significant improvements in the accuracy of execution and overall system reliability. Advanced fault observability mechanisms have also been integrated to provide system monitoring and facilitate comprehensive error characterization. HARV-SoC is being validated onboard the ROBUSTA-3A Cubesat mission, launched in June 2024.