Frontgrade Gaisler: NOEL-V RISC-V CPU & Tessent EA

This session presents a real-world integration of Siemens Tessent Embedded Analytics into a RISC-V processor and its deployment at SoC level. It describes how E-Trace execution trace capabilities were integrated into the NOEL-V processor and validated in simulation using Siemens tools.

The session then covers system-level integration in the GR765 ASIC, a space-oriented multicore RISC-V and SPARC SoC, focusing on the configuration of Tessent Embedded Analytics IPs and architectural decisions, including the integration of communicators for control and trace offload within the SoC.

Finally, the presentation describes execution trace extraction flows using external Lauterbach hardware tools via JTAG and PCIe. Key lessons learned from the integration are shared, providing practical insight for teams considering execution trace capabilities in complex SoCs.