DVCon 2022: Introduction to RISC-V CPU design verification | Imperas
DVCon 2022
Abstract:
With all the design flexibility and innovations supported by the open standard ISA of RISC-V, quality processor verification is now another flexible option. This talk gives an introduction and overview of the Imperas presentations and announcements at DVCon 2022.
Speaker: Kevin McDermott – Imperas Software
The PDF of the slides used in this talk are available at this link
This DVCon presentation can be viewed on the YouTube channel for Imperas here.
Read more here: Source link