Digital Signal Processing Accelerator for RISC-V.

%0 Conference Paper
%1 conf/icecsys/CalicchiaCCNFNR19
%A Calicchia, L.
%A Ciotoli, V.
%A Cardarilli, Gian Carlo
%A Nunzio, Luca Di
%A Fazzolari, Rocco
%A Nannarelli, Alberto
%A Re, Marco
%B ICECS
%D 2019
%I IEEE
%K dblp
%P 703-706
%T Digital Signal Processing Accelerator for RISC-V.
%U dblp.uni-trier.de/db/conf/icecsys/icecsys2019.html#CalicchiaCCNFNR19
%@ 978-1-7281-0996-1

@inproceedings{conf/icecsys/CalicchiaCCNFNR19,
added-at = {2020-09-05T00:00:00.000+0200},
author = {Calicchia, L. and Ciotoli, V. and Cardarilli, Gian Carlo and Nunzio, Luca Di and Fazzolari, Rocco and Nannarelli, Alberto and Re, Marco},
biburl = {https://www.bibsonomy.org/bibtex/20ee8c89d6fec26099c56585ac82d2830/dblp},
booktitle = {ICECS},
crossref = {conf/icecsys/2019},
ee = {https://doi.org/10.1109/ICECS46596.2019.8964670},
interhash = {1b27428e28d0c49edfe53a9cc9e28650},
intrahash = {0ee8c89d6fec26099c56585ac82d2830},
isbn = {978-1-7281-0996-1},
keywords = {dblp},
pages = {703-706},
publisher = {IEEE},
timestamp = {2020-09-09T14:54:23.000+0200},
title = {Digital Signal Processing Accelerator for RISC-V.},
url = {http://dblp.uni-trier.de/db/conf/icecsys/icecsys2019.html#CalicchiaCCNFNR19},
year = 2019
}