digital logic – How many cycles of instructions are needed to execute RISC-V in a single cycle processor?

The state machine for the PicoRV32 processor seems to require four cycles minimum

If it has a control FSM it is not a “single-cycle” processor, according to the simplified and didatical reference architecture presented in the Harris’ books. I’ve also failed to find in the PicoRV32 documentation a claim that it is a “single-cycle” micro-architecture in the same sense.

Check this section at the RISC-V version of the book (mostly the same in the other versions I know):

7.3.5 Performance Analysis

Recall from Equation 7.1 that the execution time of a program is the
product of the number of instructions, the cycles per instruction, and
the cycle time. Each instruction in the single-cycle processor takes one
clock cycle, so the clock cycles per instruction (CPI) is 1. The cycle time
is set by the critical path. In our processor, the lw instruction is the most
time-consuming and involves the critical path shown in Figure 7.17. As
indicated by heavy blue lines, the critical path starts with the PC loading a new address on the rising edge of the clock. The instruction memory
then reads the new instruction (1), and the register file reads rs1 as SrcA. While the register file is reading (2), the immediate field is sign-extended based on ImmSrc and selected at the SrcB multiplexer (path highlighted in gray). The ALU adds SrcA and SrcB to find the memory address. The data memory reads (3) from this address, and the Result multiplexer selects ReadData as Result. Finally, Result must set up at the register file before the next rising clock edge so that it can be properly written. (4)

(1) The instruction memory used is read only and combinational

(2) Also a combinational read from the register

(3) The read operation of the data memory is also combinational

(4) At the next clock edge, the result will be stored and the next instruction will be loaded

Referenced Figure (red markings on the synchronous parts are mine):

Full reference: “Digital Design and Computer Architecture – RISC-V Edition”, Sarah L. Harris, David Harris, 2022