cpu architecture – Why does RISC-V ‘J-immediate’ encode imm[11] in inst[20]?

Recently I was learning COD book by David A. Patterson, and was stuck by some questions.
Why RISC-V ‘J-immediate’ put imm[11] in inst[20] instead of inst[24]?

Is it related with detailed circuit design, if so, Could someone offer reference link or better with more helpful explanation based on the specific circuit design?

I found valuable resources answering related questions about (S)B-immediate and also read some references like page 17 in official doc volume 1.