BSC Training Course: RISC-V principles for understanding how to freely develop new solutions

• Day 1: RISC-V Fundamentals & OS

11:00 – 12:30 RISC-V ecosystem and ISA Basics / RISC-V@BSC / structure of the course

12:30 – 14.00 Lunch Break

14.00 – 15.30 Booting a RISC-V compliant OS using QEMU

15.30 – 15:45 Afternoon Break

15:45 – 17:15 Hands-on

• Day 2: RISC-V simulation with Gem-5 & QEMU

09.15 – 10:45 RISC-V simulation with Gem-5

10:45 – 11.00 Morning Break

11.00 – 12.30 hands-on

12:30 – 14:00 Lunch Break

14.00 – 15.30 The potential of custom instructions

15.30 – 15:45 Afternoon Break

15:45 – 17:15 Hands-on

• Day 3: RISC-V Vector Extension

09.15 – 10:45 Intro to RVV extension

10:45- 11.00 Morning Break

11.00 – 12:30 Exploiting RVV with the compiler

12:30 – 14.00 Lunch Break

14.00 – 15.30 Bringing RISC-V to HPC: Maturity and Methods

15.30 – 15:45 Afternoon Break

15:45 – 17:15 Hands-on