AT25SF081 SPI Flash waveform timing verification

I am again looking at Figure 11-1 Read Manufacturer and Device ID Signal for the Flash device in the title.

I have created this diagram to describe my plan for implementing this operation:

As can be seen in the diagram, my FPGA will provide the system with a 12MHz clock.

On the SI side:

• t_CLKL > 5ns
• t_CLKH > 5ns
• t_CSLS > 5ns
• t_DS > 2ns
• t_DH > 2ns

Should be satisfied as essentially all of the values CLKL, CLKH, CSLS, DSDH in my diagram above evaluate to around 42ns.

On the SO side:

Should be satisfied, as I am trying to initiate a sample from the SO line exactly at a falling edge.

I.e. V = 0ns, DIS = 0ns

Have I made a mistake here?