Optimized reversible QCA full adder subtractor for low latency and energy efficiency

Quantum-dot Cellular Automata (QCA) offer a promising beyond-CMOS platform for ultra-low-power and high-density nanoscale logic. However, existing reversible full adder/subtractor (FA/FS) designs typically suffer from high cell count, multilayer routing, multiple garbage outputs, and increased latency, limiting their practical integration into larger reversible systems. This paper presents a compact and fully reversible QCA-based FA/FS architecture constructed using a Feynman gate and a Reversible Quantum Gate (RQG), both optimized for single-layer implementation. The proposed design minimizes overhead by requiring only one constant input and producing a single garbage output while avoiding complex wire-crossing structures through the use of rotated cells. To demonstrate scalability, a 2-bit FA/FS architecture is also developed by cascading the proposed 1-bit unit. Functional verification was performed using QCADesigner, and energy dissipation was evaluated using QCAPro. The comparative analysis demonstrated that the proposed reversible FA/FS architecture provides substantial improvements over state-of-the-art reversible FA/FS designs. Specifically, the proposed circuit achieves reductions of up to 70.1% in cell count, 75% in occupied area, 57.14% in latency, and 95.4% in computational cost. In addition, the proposed architecture exhibits the lowest leakage energy and switching energy among the considered designs across the evaluated operating conditions. These improvements indicate enhanced area and computational efficiency while reducing energy-related overheads. These results highlight the suitability of the proposed FA/FS unit for future energy-efficient QCA-based arithmetic and logic systems.