Using a Performance Model to Implement a Superscalar CVA6

How does performance modeling accelerate real hardware innovation in open RISC-V designs?

In this paper, Thales demonstrates a performance model of the CVA6 RISC-V processor, built to evaluate performance-related modifications before implementing them in RTL. 

By creating a precise cycle-based Python model (99.2% accuracy on Coremark) to detect and fix performance bugs, they guided the implementation of a dual-issue CVA6 core.

The result: +40% higher CoreMark/MHz performance with only a small power (+7%) and area (+11%) increase.