RISC-V Processor Design: A Comparative Analysis of HDL Versus HLS Techniques

RISC-V, a modern open-source Instruction Set Architecture (ISA), is gaining significant traction in the computing landscape, particularly for Internet-of-Things (IoT) and System-on-Chip (SoC) applications. The increasing adoption of RISC-V has driven interest in leveraging field-programmable gate arrays (FPGAs) as a flexible, cost-effective solution for implementing custom hardware. However, conventional hardware description languages (HDLs) require extensive expertise and development time, prompting the exploration of High-Level Synthesis (HLS) as an alternative. This study presents a comparative analysis of HLS and HDL in implementing a RISC-V processor supporting the RV32I instruction set. The comparison is based on firmware development time, measured by lines of source code (LCS), and FPGA resource utilization. The findings reveal that HLS reduces the LCS by 65%, significantly accelerating development. However, it also results in over three times higher lookup table (LUT) usage and nearly double the flip-flop consumption of HDL. While both methods successfully synthesize and function correctness is ensured through behavioral simulation of the RISC-V ISA, the resource efficiency of HDL allows for the implementation of additional parallel ISAs, which HLS struggles to accommodate due to its higher resource demands. Therefore, while HLS proves advantageous for rapid development, HDL remains indispensable for applications requiring optimal performance and efficient resource utilization.