Difference of ‘software interrupt’ and ‘exception’ in RISC-V
I’m reading privileged ISA manual of RISC-V, and I found that they strictly separate the ‘interrupt’ and ‘exception’ and ‘trap’. In my understanding, the asynchronous event from outside is ‘interrupt’, and unexpected situation by instruction execution is ‘exception’. And ‘trap’ is context switching by both ‘interrupt’ and ‘exception’.
And I found other terms, ‘hardware interrupt’, ‘software interrupt’ and ‘timer interrupt’. I understand that the timer interrupt needs to be managed separately because it’s important. However, I can’t understand what ‘software interrupt’ is. I found these terms at the description about mcause, mideleg and mie registers. Here’s the table.
In my guess, I think ‘exception’ is different from ‘software interrupt’ because in the table, there’re distinct entries for ‘software interrupt’ and other not-interrupt events such as ‘instruction access fault’ or ‘illegal instruction’ which I thought would be the examples of ‘exception’.
Can anyone explain about what exactly this ‘software interrupt’ is?
And if it’s different from the ‘exception’, then is mie register not responsible for enabling any ‘exceptions’?
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