gbellocchi/xil_open_hw_23: GenOv: Streamlining the Design and Optimization of Heterogeneous RISC-V-based FPGA Overlays
Project name: GenOv: Streamlining the Design and Optimization of Heterogeneous RISC-V-based FPGA Overlays
Team Number: xohw23-150
Team: Gianluca Bellocchi, Alessandro Capotondi
Supervisor: Andrea Marongiu
If you want to use GenOv and the other released items, you can cite our paper [1].
GenOv is an open-source design automation tool to seamlessly generate and optimize heterogeneous FPGA overlays built around the RISC-V instruction set architecture (ISA). [1].
It offers plug-and-play integration of HLS-compiled IPs given a customizable accelerator interface – or accelerator wrapper – which provides shared-memory communication to the overlay cores.
Our FPGA overlays are an extension of HERO, an open-source research platform for heterogeneous multi-/many-core architectures based on the Parallel Ultra Low Power (PULP) Platform [2,3].
The repository is organized in the following way.
| Platform | Description |
|---|---|
| genov/ | Repository of GenOv, a design automation tool to generate and specialize heterogeneous RISC-V-based FPGA overlays [1]. |
| benchmarks/ | Set of Matrix Multiplication (MatMul) implementations to show off the advantages of our FPGA overlay solution. |
| ex-prj-zcu102/ | An exemplary implementation of our FPGA overlay integrating a HLS-based MatMul accelerator. The folder comprises HW/SW project files, as well as a ready-to-use SD card image for Zynq UltraScale+ MPSoC ZCU102 boards. |
| hw/ | Hardware subsystem. |
| third-party/ | Third-party repositories. |
We include a TUTORIAL to guide the user in its first steps using GenOv.
This will provide a baseline understanding of how to:
- Build and run the provided MatMul benchmarks;
- Deploy the pre-built ZCU102 image under ex-prj-zcu102/;
- Reuse the proposed approach for other projects.
- “A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment” – G. Bellocchi et al. (2021)
- “HERO: An open-source research platform for HW/SW exploration of heterogeneous manycore systems” – A. Kurth et al. (2018)
- “PULP: A parallel ultra low power platform for next generation IoT applications” – D. Rossi et al. (2015)
Read more here: Source link