Tag: SiFive
KVM RISC-V Conditional Operations [LWN.net]
From: Anup Patel <apatel-AT-ventanamicro.com> To: Paolo Bonzini <pbonzini-AT-redhat.com>, Atish Patra <atishp-AT-atishpatra.org>, Palmer Dabbelt <palmer-AT-dabbelt.com>, Paul Walmsley <paul.walmsley-AT-sifive.com>, Conor Dooley <conor-AT-kernel.org>, Rob Herring <robh+dt-AT-kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt-AT-linaro.org>, Shuah Khan…
KVM RISC-V ONE_REG ISA extension improvements [LWN.net]
From: Anup Patel <apatel-AT-ventanamicro.com> To: Paolo Bonzini <pbonzini-AT-redhat.com>, Atish Patra <atishp-AT-atishpatra.org> Subject: [PATCH 0/7] KVM RISC-V ONE_REG ISA extension improvements Date: Wed, 12 Jul 2023 21:40:40…
Add timer driver for StarFive JH7110 RISC-V SoC [LWN.net]
From: Xingyu Wu <xingyu.wu-AT-starfivetech.com> To: <linux-riscv-AT-lists.infradead.org>, <devicetree-AT-vger.kernel.org>, “Daniel Lezcano” <daniel.lezcano-AT-linaro.org>, Thomas Gleixner <tglx-AT-linutronix.de>, Krzysztof Kozlowski <krzysztof.kozlowski+dt-AT-linaro.org> Subject: [PATCH v3 0/3] Add timer driver for StarFive JH7110 RISC-V…