Tag: RISC-V
enable -smbios option on RISC-V
With SMBIOS support added for RISC-V we also should enable the command line option. Signed-off-by: Heinrich Schuchardt <heinrich.schucha…@canonical.com> — v2: new patch — qemu-options.hx | 2 +- 1 file changed,…
KVM RISC-V Conditional Operations [LWN.net]
From: Anup Patel <apatel-AT-ventanamicro.com> To: Paolo Bonzini <pbonzini-AT-redhat.com>, Atish Patra <atishp-AT-atishpatra.org>, Palmer Dabbelt <palmer-AT-dabbelt.com>, Paul Walmsley <paul.walmsley-AT-sifive.com>, Conor Dooley <conor-AT-kernel.org>, Rob Herring <robh+dt-AT-kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt-AT-linaro.org>, Shuah Khan…
riscv – RISC-V GCC missing mm_malloc.h
I downloaded RISC-V cross compilers on a x86 Ubuntu following the instructions: github.com/riscv-collab/riscv-gnu-toolchain I’m trying to compile code that compiles fine in the native GCC installation version 9.4, but in…
Add host ticks function for RISC-V
Signed-off-by: LIU Zhiwei <zhiwei_…@linux.alibaba.com> — v2: 1) Use rdtime instead of rdcycle for dynamic cpuclk adjustment. 2) Read timeh twice in case of time overflow for 32-bit cpu. — include/qemu/timer.h…
Milk-V Meles Single Board Computer launched equipped with RISC-V processor
Read more here: Source link
[valgrind] [Bug 468979] Add support for RISC-V vector instructions
bugs.kde.org/show_bug.cgi?id=468979 — Comment #1 from JojoR <rjie…@gmail.com> — Hi, We are glad to open source RVV implementation here: github.com/rjiejie/valgrind-riscv64 4 kinds extra ISAs were added in this repo: RV64Zfh :…
KVM RISC-V ONE_REG ISA extension improvements [LWN.net]
From: Anup Patel <apatel-AT-ventanamicro.com> To: Paolo Bonzini <pbonzini-AT-redhat.com>, Atish Patra <atishp-AT-atishpatra.org> Subject: [PATCH 0/7] KVM RISC-V ONE_REG ISA extension improvements Date: Wed, 12 Jul 2023 21:40:40…
Add timer driver for StarFive JH7110 RISC-V SoC [LWN.net]
From: Xingyu Wu <xingyu.wu-AT-starfivetech.com> To: <linux-riscv-AT-lists.infradead.org>, <devicetree-AT-vger.kernel.org>, “Daniel Lezcano” <daniel.lezcano-AT-linaro.org>, Thomas Gleixner <tglx-AT-linutronix.de>, Krzysztof Kozlowski <krzysztof.kozlowski+dt-AT-linaro.org> Subject: [PATCH v3 0/3] Add timer driver for StarFive JH7110 RISC-V…
correct stack pointer if enable ARCH_KERNEL_STACK
This is an automated email from the ASF dual-hosted git repository. xiaoxiang pushed a commit to branch master in repository gitbox.apache.org/repos/asf/nuttx.git The following commit(s) were added to refs/heads/master by this…
GCC 13.1 Released
GCC 13.1 Released Richard Biener rguenther@suse.de Wed Apr 26 08:20:42 GMT 2023 The GCC developers are proud to announce a new major GCC release, 13.1. This release integrates a frontend…
Basic pinctrl support for StarFive JH7110 RISC-V SoC [LWN.net]
From: Hal Feng <hal.feng-AT-starfivetech.com> To: <linux-riscv-AT-lists.infradead.org>, <devicetree-AT-vger.kernel.org>, <linux-gpio-AT-vger.kernel.org> Subject: [PATCH v4 0/4] Basic pinctrl support for StarFive JH7110 RISC-V SoC Date: Fri, 03 Feb 2023 22:17:57…