I am using Quartus Prime Lite 19.1.0. module memory_address_register1 #( parameter ADDR_WIDTH = 4 )( input clk, rst, load, input [ADDR_WIDTH-1:0] add_in, output reg [ADDR_WIDTH-1:0] add_out ); always @(posedge clk)…Read moreverilog – Capturing the right posedge clock in Quartus waveform