Investigation of breakdown voltage degradation in low-voltage narrow gate trench MOSFET by edge termination optimization

In this paper, we investigate breakdown voltage degradation in a 25 V low-voltage narrow gate (NG) shield-gate trench MOSFET (NG-SGTMOS). Experiments and simulations based on Technology Computer-Aided Design (TCAD) indicate that electric field crowding and parasitic bipolar junction transistor (BJT) punch-through are responsible for the degradation of the device breakdown characteristic. To address these issues, two critical parameters, t1 and t2, are optimized in the layout of the transition and termination regions of the experimental NG-SGTMOS. It is demonstrated that electric field crowding induced by excessive and non-full depletion in edge termination is successfully eliminated at t1 = 0.6 μm. Moreover, when improving t2 beyond 0.2 μm, the soft breakdown characteristic owing to parasitic npn-BJT punch-through can be suppressed. As a result, the breakdown voltage stability of the proposed low-voltage NG-SGTMOS is improved.

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